The present invention relates to a RAKE receiver structure and, more particularly, to a RAKE receiver with minimal area, gate delay and power requirements accomplished by implementing the RAKE receiver as a transverse correlator in the complex domain.
In CDMA receivers, one of the most important units is the RAKE receiver. In particular, a RAKE receiver contains a matched filter which resolves the multi-path components of the incoming signal. Additionally, the RAKE receiver must match the incoming signal to a local user code to authenticate reception. The matched filter achieves this result by correlating the received signal x(n) with a buffered sequence s(n) defined as a pseudo-random noise (PN) sequence.
In most conventional implementations of the RAKE receiver, the correlation length is usually large, where the actual size depends on the particular function for the correlator output. In many circumstances, the length may be as large as 512 samples. The correlation operation is very similar to the Finite Impulse Response (FIR) filter operation. Consequently, the problems associated with implementing the correlator in silicon are similar to implementing FIR filters with a large number of coefficients. Implementation becomes more difficult since addition and subtraction operations for the correlator are defined in the complex domain. Moreover, the correlator is the most active component of the RAKE receiver and is a major drain on the battery power in a mobile terminal.
These and other RAKE receiver problems present in the prior art are addressed by the present invention, which relates to a RAKE receiver structure and, more particularly, to a RAKE receiver with minimal area, gate delay and power requirements accomplished by implementing the RAKE receiver as a transverse correlator in the complex domain.
In accordance with the present invention, the RAKE receiver correlator comprises a transverse correlator formed as a serial plurality of N functional units, each functional unit comprising a multiplier, an adder and a memory device (e.g., D flip-flops). The received signal is applied as an input to each multiplier, where the remaining input is a single bit of a local pseudo-random sequence s(n). The product is then added to all the products from each previous stage to form the xe2x80x9cintermediatexe2x80x9d correlation product Rxs for that stage. Therefore, in accordance with the present invention, the required addition is spread out over each stage of multiplication.
In a preferred embodiment of the present invention, the received signal x(n) and sequence s(n) are parsed into a pair of complex I and Q components. Each functional unit is then configured to separately process the I and Q rail information. Since the same operations are performed on each component, the same functional unit may be used to form each component by incorporating a mulitplexer to control the inputs (i.e., either xe2x80x9cIxe2x80x9d or xe2x80x9cQxe2x80x9d) applied to each functional unit.
In association with another feature of the present invention, an m-bit carry-save adder may be used in place of a conventional carry-propagate adder. In this form, the switching activity, and therefore power, is minimized (since the carry bits do not need to propagate along the entire m-bit length of the addition at each stage). That is, the final xe2x80x9csumxe2x80x9d is performed only at the last stage.
Other and further features of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.